Model reduction : an ICT application

The demand for reliable model reduction algorithms in ICT engineering application fields has been continuously increasing over the last few years, and is expected to grow even further in the future. In fact, precisely this area has been very inspirational for developments in model order reduction. Design flows for present and future hardware architectures are more and more based on systemlevel approaches that include all parasitics and second-order effects into consideration during computer-based simulation and prototyping, thereby constituting an extremely challenging problem that cannot be handled by available software. The only viable solution for the simulation of the resulting large dynamical systems is to resort to model compression and order reduction.

Among the most critical aspects that need advancement with respect to the available state of the art are:

  • Model reduction of systems characterized not only by a large number of states, but also a large number of inputs and outputs. As an example, verification of mixed power/signal distribution networks requires accurate characterization of systems with several hundreds of interface ports.
  • Guaranteed passive macro model extraction from frequency and time-domain responses, possibly under parameter variation and uncertainties. Although passive macro modelling from measurements is a relatively mature field, the extension to the parametric case is still not mature for routine application in system design and optimization.
  • Compact dynamical modelling of both weakly and strongly nonlinear circuit blocks in digital, analog, and analog/mixed signal systems as found in portable devices of present and future generation, for which current simulation methodologies are based on extremely inefficient full transistor-level extracted netlists.

To address these problems, mathematicians and engineers need to work closely together. Automatic model reduction techniques for strongly nonlinear devices and circuit blocks are needed based on tensor approximations or on extensions of the recently developed and promising POD-DEIM method. An additional complication is the fact that designers in industry are changing the classical way of design, and making more and more use of parameterized cells. This means that the model reduction techniques need to be able to deal with parameterized models. Other groups will provide the algorithms for the stochastic aspects of the problem, for the reduction of the large networks with many ports by techniques inspired by graph theory. Important is also that the techniques are suitable for use on modern computer architectures, requiring again a different skill. Clearly, this cannot be addressed by a single team, but only by a coordinated larger scale effort. Software vendors, supplying the electronics industry with tools, are extremely interested in such methods.